module always_ff_process;

logic [7:0] a, b, sum;
logic clk = 0;
logic rst = 0;

always_ff @(posedge clk) begin
    if (rst) begin
        sum <= 0;
    end
    else begin
        sum <= a + b;
    end
end

initial begin
    $monitor ("@%g\tclk = %b rst = %b, a = %d b = %d sum = %d", $time, clk, rst, a, b, sum);
    #1 rst = 1;
    #5 rst = 0;
    #1 a = 1;
    #1 b = 1; 
    #5 a = 10;
    #1 $finish;
end

always  #1  clk = ~clk;

endmodule
